Silimate is the copilot for chip designers. Chip teams today are still using the same archaic workflows from 30 years ago, resulting in lengthy 12-18 month design cycles and the inability to ship chips fast enough to keep up with the software pointer. We're changing that at Silimate. Our chip design copilot is helping chip designers write correct, PPA-optimized RTL code from the onset, and build better chips in less time. We're building a catalytic tool for the chip industry. We're well-funded by top investors and are generating revenue with customers that are world-class chip and IP design companies. We're growing fast — demand for Silimate has outpaced our ability to build and ship the product. We're looking for talented engineers that are passionate about the semiconductor chip space to join us. We’re looking for a passionate founding engineer that has significant AI/ML + LLM experience to build the co-pilot for chip designers with us. Who you are: You’re excited about transforming the way chips are built by the entire industry, and enabling new levels of dynamism and speed for the hardware compute ecosystem. You’ll leverage your AI/ML + LLM expertise to develop key co-pilot features that make building chips much faster, easier, and more intuitive. You’ll also work directly with our world-class customers building advanced chips and IP to iterate on our product with user feedback. We ship product updates on a weekly basis, work in-person together in the Bay Area, and geek out about semiconductor news/technology advances. If this sounds like you, please apply to join the team! What you’ll do: Develop AI models/infrastructure that ship to 10+ chip/IP customers Make architectural decisions for key product features Translate user feedback into product updates/features Plan core product roadmap and strategy with the founders Develop AI models/infrastructure that ship to 10+ chip/IP customers Make architectural decisions for key product features Translate user feedback into product updates/features Plan core product roadmap and strategy with the founders Minimum requirements: Highly skilled with Python, C++, PyTorch/torch Good understanding of traditional ML models, LLMs, foundation models, and agents Experience building ML pipelines Experience fine-tuning and benchmarking LLMs/foundation models Excited about applying AI/ML techniques to chip design Good at shipping high-quality code quickly Resilient, data-driven, and works from first principles Highly skilled with Python, C++, PyTorch/torch Good understanding of traditional ML models, LLMs, foundation models, and agents Experience building ML pipelines Experience fine-tuning and benchmarking LLMs/foundation models Excited about applying AI/ML techniques to chip design Good at shipping high-quality code quickly Resilient, data-driven, and works from first principles Ideal requirements: Have shipped product using LLMs, foundation models, and/or agentic workflows Experience with AWS SageMaker Have shipped product using LLMs, foundation models, and/or agentic workflows Experience with AWS SageMaker Nice-to-have requirements: Experience with AI/ML-driven chip EDA software tooling (either open-source or commercial tools) Experience with designing chips (either open-source or commercial designs) Experience with AI/ML-driven chip EDA software tooling (either open-source or commercial tools) Experience with designing chips (either open-source or commercial designs) Benefits: Generous salary and equity package Full health/vision/dental/401k benefits Generous salary and equity package Full health/vision/dental/401k benefits
Full-time
$125K–$157K
Mountain View, CA, US, San Francisco, CA, US
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