About the Role

ASIC Design Engineer responsible for designing and optimizing hardware for AWS machine learning servers, including AWS Inferentia. The role involves integrating subsystems into SoCs, implementing RTL, and working with cross-functional teams to deliver high-performance, power-efficient designs.

Key Responsibilities

• Integrate multiple subsystems into top-level SoC, ensuring correct clock/reset/functional/DFT signal routing
• Implement and deliver high-performance, area and power-efficient RTL to achieve design targets
• Analyze design, microarchitecture or architecture to make trade-offs based on requirements
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design
• Perform lint and clock domain crossing quality checks on the design

Required Skills & Qualifications

Must Have:

• BS degree in electrical engineering or equivalent
• 3+ years in RTL design for SoC
• 3+ years of VLSI engineering
• 3+ years with code quality tools including Spyglass, LINT, or CDC

Nice to Have:

• Experience scripting for automation (e.g., Python, Perl, Ruby)
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
• Familiarity with data path design, interconnects, AXI protocol

Benefits & Perks

• Work-life harmony with flexible working culture
• Inclusive team culture with employee-led affinity groups
• Mentorship and career growth opportunities
• Competitive compensation with base pay ranging from $129,800 to $212,800/year
• Comprehensive benefits including medical, financial, and equity