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About the role

Senior Engineer - Design for Test (DFT) at Microsoft

Required Skills

dftatpgjtagmemory bistverilogsystem verilogeda toolstclperl

About the Role

Senior DFT Engineer responsible for developing test solutions for Microsoft's silicon chips, ensuring DFX goals are met, and collaborating with cross-functional teams. The role involves owning DFT specifications, enhancing tools, and enabling silicon bring-up.

Key Responsibilities

  • Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products
  • Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested
  • Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI
  • Provide test plans and engage closely with verification engineers to perform waveform reviews
  • Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis

Required Skills & Qualifications

Must Have:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree AND 4+ years OR Bachelor's Degree AND 5+ years OR equivalent experience
  • 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
  • ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
  • Ability to meet Microsoft, customer and/or government security screening requirements including Microsoft Cloud Background Check

Nice to Have:

  • Experience with Test Chip development and some unique challenges it brings about for DFT
  • Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits
  • Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax

Benefits & Perks

  • Industry leading healthcare